Projects

This project implements the transformer scaled dot-product attention kernel: Attention(Q,K,V)=softmax(QKᵀ/√d_k)·V , directly in synthesizable Verilog for FPGA/ASIC targets. The design processes a 4×8 (sequence length × embedding dimension) tokenized input in Q4.4 fixed-point arithmetic (8-bit signed with 4 fractional bits), computing the full attention computation through a 12-phase finite state machine (FSM) that time-multiplexes a single 20-bit signed MAC unit across all five matrix multiplications (Q, K, V projections; QKᵀ scoring; O=WV output). The softmax uses a 9-entry piecewise LUT for exp(x) with row-max subtraction for numerical stability, and a combinational integer divider for normalization.

A sensor-aware adaptive extension of LGCP-based barrier coverage that reweights trajectory intensity toward low-detection paths conditioned on sensor deployment, enabling realistic modeling of evasive adversarial targets (drones, UAVs). From β = 0 to β = 5, the adaptive-aware method degrades by only 0.084 vs. 0.297 for the baseline, yielding ~11% fewer expected missed trajectories at β = 5.

DroneSeg is a full-stack semantic segmentation platform for drone/aerial imagery. Upload drone photos, run SegFormer-B2 deep learning inference to generate land-cover classification masks with bounding boxes and visualize results on an interactive map and GeoJSON export. This is an MVP application built for demo.

ARScaner is a SwiftUI-based iOS application that harnesses Apple's Object Capture and Photogrammetry APIs to perform real-time 3D reconstruction. By integrating LiDAR sensor data with multi-view stereo algorithms, it generates detailed USDZ models from captured image sequences, offering superior accuracy and resolution compared to traditional camera-only scanning methods.

Smart Fridge monitors your fridge about temperature and humidity, alerts you when food is about to expire, or when someone steals your food. In addition, it can generate a recipe based on items in the fridge with the help of OpenAI API.

Implemented the VCFP (Voice Command Fingerprint) attack and BuFLO defense to analyze voice assistant network traffic, showing how encrypted packets can reveal voice commands and how BuFLO mitigates this traffic analysis.

This is a 28.9 million parameter language model that generates text on an ESP32-S3 microcontroller. It runs on the chip itself, with nothing sent to a server, and it displays generated text at 10.44 tokens per second.It fits because most of the model lives in flash instead of RAM, using Per-Layer Embeddings, an idea from Google's Gemma 3n.

Implemented a novel hybrid deep learning architecture that uniquely combines the strengths of Convolutional Neural Networks (CNNs) and Vision Transformers (ViT) for medical image classification.

Implemented a high-performance medical assistant based on the Qwen2-0.5B-Instruct architecture. It is optimized via 4-bit QLoRA and implements Kahneman-Tversky Optimization(KTO) continuous learning pipeline that refines model behavior through real-time human preference data.

Optimized a high-performance RAG pipeline (Corrective RAG) utilizing the Llama-3.2-3B LLM, achieving a 70% reduction in memory requirements (from 12GB to 3.5GB) using 8-bit quantization (llama.cpp backed) while maintaining 99.5% of the original model's performance.

ALTM has Agentic Routing (PageIndex), Dynamic Importance Decay, and Automated Memory Merging to ensure your agents remember what matters and forget what doesn't.

A research project exploring automated generation of chest X-ray diagnostic reports using various Vision-Language Models (VLMs) and CNN backbones with distillation and finetuning.

Developed an end-to-end computer vision system combining YOLOv8 for real-time refrigerator detection, CLIP embeddings for feature extraction, and Qdrant vector database for similarity search.

Early and Late Fusion techniques for multimodal hateful meme classification by integrating visual features from pretrained CNNs with textual features from pretrained BERT models.

Implemented Early Fusion with BiLSTM, CNN, and LSTM+CNN and Late Fusion by concatenating the output of BiLSTM, CNN, and BiLSTM+CNN.

Static Random-Access Memory (SRAM) cells, which act as quick and effective memory storage components, are crucial components of contemporary digital integrated circuits. In this report, 1-Bit SRAM cell is implemented and its schematic, simulation results, truth tables, and stick diagram is analyzed. The performance characteristics of the SRAM cell, including delay and power consumption, are carefully analyzed using comprehensive simulations using cadence virtuoso. The outcomes show that the 1-bit SRAM cell provides competitive performance traits while taking up only a little amount of space.

The objective of this project was to design and implement a fully operational SAP-1 (Simple-As-Possible) microprocessor architecture using Logisim, integrating both hard- ware and software components for automatic program execution. The processor was constructed from fundamental digital modules including the general-purpose register, arithmetic logic unit (ALU), 5-to-32 decoder, SRAM memory block, instruction register, ring counter, program counter, and control sequencer . Additional subsystems such as the barrel shifter and ring rotator were implemented to support extended logical and data manipulation operations.
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Developed an AI-based-voice controlled over-the-internet Automatic Warehouse Switching and Monitoring system.